Intel has delayed a high-end server chip, billed as the world's first 2 billion transistor microprocessor, originally expected as long ago as 2007.  Tukwila is a quad-core update to the Itanium processor, which has had a less-than-promising run since the original version was announced back in 2001. The chip's architecture--based on explicit instruction-level parallelism--is a radical departure from the x86 design used in PCs today. It was believed at one time that Itanium would replace x86 chips in many Intel-based computers.

So, what's delaying it this time? Intel has "made some engineering enhancements to the Tukwila platform," according to a statement Thursday from Intel. As one enhancement, Tukwila and its follow-on processors on the Itanium roadmap, Poulson and Kittson, will be socket compatible. Intel is also introducing a technology called "scalable buffered memory" to Tukwila platforms. Scalable buffered memory enables higher memory capacities and uses newer DDR3 (Double Data Rate, third generation) memory.

The number of CPU pins that can be dedicated to a memory interface is limited. Scalable buffered memory acts as a memory expander by connecting to multiple DDR3 RDIMMs (Registered Dual In-line Memory Modules) for each CPU memory interface, thus increasing the total memory capacity compared to natively attached memory configurations, according to an explanation provided by Intel. "Validation testing of the Tukwila processor with the new memory will move the Tukwila platform launch from early '09 to mid '09," and Intel spokesperson said.