Ars Technica has an interesting article on a new 64-core CPU designed by Tilera. The TILE64 chip is aimed at embedded applications, so don't expect to see it pop up in desktops anytime soon. However, Tilera's director of marketing, Bob Dowd, told Ars that TILE64 represents a 'sea change in the computing industry,' and the company's CEO isn't shy about pitching the chip as the 'first significant new chip architectural development in a decade.'

But the basic tile + processor/cache + router + mesh network idea was pioneered by Dr. Agarwal and MIT's RAW project about a decade ago, and now those same ideas also form the basis for TILE64. TILE64 consists of a mesh network of 64 tiles, with each tile containing a general-purpose processor core and a non-blocking router. The short-pipeline, in-order, three-issue cores implement a MIPS-derived VLIW ISA with a few important and peculiar features.

Sounds like a promising concept. It would be quite interesting to see algorithm for scheduling tasks that also takes into account "tile hops".