The company has begun tests on prototypes of the polymorphic MONARCH processors to verify they'll function as designed and to establish their maximum throughput and power efficiency. MONARCH, containing six microprocessors and a highly interconnected reconfigurable computing array, provides 64 gigaflops (floating point operations per second) with more than 60 gigabytes per second of memory bandwidth and more than 43 gigabytes per second of off-chip data bandwidth.

The MONARCH processor was developed under a Defense Advanced Research Project Agency (DARPA) polymorphous computing architecture contract from the U.S. Air Force Research Laboratory. Raytheon Space and Airborne Systems led an industry team with the Information Sciences Institute of the University of Southern California to create the integrated large-scale system on a chip with a suite of software development tools for programs of high value to the Department of Defense and commercial applications. Besides USC major subcontractors included Georgia Institute of Technology, Mercury Computer Systems and IBM's Global Engineering Solutions division.