TSMC and Nvidia today announced that TSMC has successfully produced a fully-functional sample of a graphics chip for handheld devices with embedded DRAM. While there are no details about the product, it once again shows the interest of a leading graphics chips designer towards the eDRAM technology.

TSMC's 65nm embedded DRAM process and IP shrinks the cell and macro size by nearly 50 percent compared to its previous generation. The foundry is targeting the higher bandwidth offered by the embedded DRAM at applications such as game consoles, high-end networking, digital consumer, and multimedia processors. The embedded DRAM allows for some of the key power-saving tricks being tapped by designers today, including sleep mode, partial power cut-off and on-chip temperature compensation, while also improving data retention time. The 65-nm embedded DRAM process is built on up to 10 metal layers using copper low-k interconnect and nickel silicide transistor interconnect, the company said. The cell size is less than a quarter of its SRAM counterpart, and macro densities range from 4Mbits to 256Mbits. TSMC began its 65-nm logic production in the second quarter of 2006. It's 90-nm embedded DRAM process has run since the first quarter of 2006.